The present invention relates generally to a method and apparatus for manufacturing a semiconductor integrated circuit (xe2x80x9cICxe2x80x9d). More specifically, this invention relates to an improved method and apparatus for processing semiconductor wafers with a dual track and stepper.
The present invention applies particularly to the fabrication of semiconductor integrated circuits. Some examples of these semiconductor integrated circuits comprise non-volatile memory integrated circuits. Non-volatile memory integrated circuits include an EPROM, an EEPROM, a flash memory device, and a complementary metal oxide silicon (xe2x80x9cCMOSxe2x80x9d) type device. Exemplary devices may comprise field-effect transistors (xe2x80x9cFETxe2x80x9d) containing a gate over gate insulator over silicon (xe2x80x9cMOSFETxe2x80x9d), as well as other ultra-large-scale integrated-circuit (xe2x80x9cULSIxe2x80x9d) systems.
Integrated circuits are utilized in a wide variety of commercial and military electronic devices, including, e.g., hand held telephones, radios and digital cameras. The market for these electronic devices continues to demand devices with a lower voltage, lower power consumption and a decreased chip size. Also, the demand for greater functionality is driving the xe2x80x9cdesign rulexe2x80x9d lower, for example, into the sub-half micron range.
These integrated circuit devices are generally fabricated in groups on a semiconductor wafer. During fabrication, a photolithographic process is utilized to form various components and structures. The components and structures are formed according to a photolithographic pattern provided on the semiconductor wafer. This photolithographic process is conventionally utilized in the front end portion of a semiconductor wafer production. There are three basic steps involved in the photolithography processing of each semiconductor wafer. First, a photoresist is applied to each wafer in a coater. Each wafer is then exposed to a radiation source in a stepper, and finally each exposed wafer is developed in a photoresist developer. Since the IC are typically multilayered, this process is repeated a number of times.
More specifically, in a portion of the photolithography of these wafers, a photoresist coater and developer system is utilized in the patterning of various layers of the wafer that will form the circuit device. The photoresist coater and developer system applies, or coats, a light-sensitive resin, i.e., a photoresist layer, to wafers by depositing a pre-selected amount of the photoresist solution. Next, the system spins the wafers at a relatively high rate of speed to distribute the photoresist into a relatively even coating over the wafer. Then, the wafers are baked to induce a volatization of a casting solvent in the photoresist. Next, the wafers are exposed to a light source in a stepper, e.g., a deep ultraviolet (xe2x80x9cDUVxe2x80x9d) light source, for patterning. The exposed wafers are then developed by a chemical treatment, and are again baked to dry the wafers.
Conventional examples of resist coater and developer systems, e.g., are the Tokyo Electron Limited (TEL) sub-half micron compatible Coater/Developer Clean Track systems. Conventional systems may include a chemically amplified resist (xe2x80x9cCARxe2x80x9d) in the deep ultraviolet (xe2x80x9cDUVxe2x80x9d) process that has been adopted for the sub-half micron design rule type of circuit devices. The combination of the coater and developer is typically referred to as a xe2x80x9ctrack.xe2x80x9d
As to the development of the photoresist that has been formed on the wafer, conventionally, a chemical developer is utilized to remove areas defined in the steps of masking and exposure of the photoresist layer that has been deposited on the wafer. The development of the photoresist is an important part of the wafer fabrication.
For example, in sub-half micron semiconductor processing, one of the most important parameters in the photolithography area is the critical dimension (xe2x80x9cCDxe2x80x9d). The above described relatively complex integrated circuits will only function as designed if the critical dimensions are within specification. There are many parameters that control the critical dimension. One of these parameters comprises the time interval between the application of the photoresist in the coater and the exposure of the wafer in the stepper.
Wafers may be processed in either a batch or interface mode. In the batch mode a number (25 for example) wafers may be processed together such that a photoresist is applied to each of the wafers individually. Depending on the process, the time between the application of the photoresist to the first wafer to be processed and the last wafer may be 45 minutes. Once the photoresist has been applied to all of the wafers, each wafer is then individually exposed in the stepper. After all of the wafers have been exposed, then each wafer is developed in the developer.
In the interface mode, each wafer is coated with a photoresist and then sent to the stepper to be exposed. Since the time interval required to expose each wafer in the stepper is less than the time required to apply the photoresist in the coater, no queue develops between the coater and the stepper. However, the time required to develop each wafer is longer than the time required to expose the wafer in the stepper. As a result a queue develops between the stepper and the developer.
As discussed above, IC""s are often multi-layered. Accordingly, once the lot of wafers has been processed, the process of photoresist application, exposure, and developing is repeated on the lot until the IC""s are completed. The type of photoresist that is applied for each layer of the IC may be different than the previous photoresists that have been applied. Additionally, a different type of photoresist may require a different developer material. For example, a track may include the ability to apply three different photoresists in a single coater, and two different developer materials in the developer. The number of photoresists and developer materials available is a function of the number of nozzles designed into the system. Additionally, a different image is used to expose the wafers for each layer of the IC. The image exposed on the wafer is formed on a reticle used in the imaging process.
Some different photoresists react with one another and coagulate. This can result in clogging the drainage of the coater station. As a result, either the drainage system must be cleaned periodically to prohibit the system from backing up, or the wafers must be processed on a separate track and stepper line.
A typical setup includes a track having a coater and a developer that is connected to a single stepper. The various components communicate via software that coordinates the processing of the wafers in the coater, stepper and developer. A conventional wafer transfer system includes a plurality of cassettes used to store the wafers both before and after they are processed in the coater, stepper or developer. In the batch mode, a group of wafers is stored in a cassette. Automated equipment moves each wafer from the cassette for processing in the given station and then replaced to the cassette when complete. The entire cassette may then be moved manually by an operator to the next station for processing. The entire system may be automated utilizing lateral feeders and conveyor belts, thereby permitting the wafers to be processed in the interface mode.
Alternatively, as described in U.S. Pat. No. 5,455,894, assigned to a common assignee, the wafer transfer system may include a computer controlled robotic interface unit having a robotic arm that moves the wafers without the need for conveyor belts. The ""894 patent is included herein by reference.
The cost of the stepper may be six time the cost of the coater and developer track unit. Since the stepper processes the wafers more quickly than the coater and developer, the stepper is often idle. Additionally, maintenance is required on the coater and developer more often than the stepper. Since the stepper is dedicated to a specific track, the stepper will be idled during the periodic maintenance for the track.
Thus, a problem exists in that the most expensive portion of the track and stepper system is idle for a period of time, both during the fabrication of the wafers and during periodic maintenance on the coater and developer units. Additionally, the number of photoresists and developers available are limited due both to the limited number of photoresist nozzles and the coagulation problem. Accordingly, more than one track and stepper line may be required for the processing of the wafers.
Accordingly, it would be desirable to develop a track and stepper system that would permit the timely processing of the wafers, that minimizes the downtime of the stepper, and that provides for a greater number of possible photoresist and developer combinations.
One embodiment of the invention relates to an apparatus for processing semiconductor wafers. The apparatus includes a first track having a first photoresist coater to apply a photoresist a first wafer. The first track also includes a first developer. A second track includes a second photoresist coater to apply a photoresist to a second wafer. The second track includes a second developer. A stepper integrated with the first and second tracks exposes the first and second wafers.
Another embodiment relates to a method for processing semiconductor wafers including coating a first set of wafers with a photoresist material in a first coater station. The first set of wafers is exposed to a light source in a stepper. The method also includes developing the first set of wafers with a developer in a first developer station. A second set of wafers is coated with a second photoresist material in a second coater station. The second set of wafers is exposed to the light source in the stepper. The method also includes developing the second set of wafers with the developer in the second developer station.
Still a further embodiment includes a method for processing semiconductor wafers comprising first selecting one of a first coater and a second coater. A first wafer is coated with a photoresist from the one of the selected first and second coaters to form a coated wafer. The coated wafer is exposed with an image in a single stepper to form an exposed wafer. One of a first developer and second developer is selected, and the exposed wafer is developed in the selected developer.
These and other benefits and features of the present invention will be apparent upon consideration of the following detailed description of preferred embodiments thereof, presented in connection with the following drawings in which like reference numerals identify like elements throughout.